技术

制造设计(DFM)

提高您的设计,避免昂贵的制造屈服损失

与制造业的早期工程参与和合作是创造可靠和成本效益设计的关键。在峰会上,我们投资于您的设计成功,并将提供复杂的凸轮工具系统和个人PCB专业知识与您合作。

数据审查- 我们的DFM报告首先在设计规则检查(DRC)算法中最佳地使用设计中所有关键属性的自动审核。此工具分析您的数据并检查其对应于IPC设计规则指南的关键设计和制造属性。我们的全面报告将为您提供以下内容:

  • 董事会大纲清关
  • 板厚度
  • 钻头直径(垫直径)
  • 钻孔铜清除
  • 导体宽度
  • 最小导线宽度
  • 追踪痕迹
  • 到垫子的间隙
  • Clearance to copper fill

根据您的需求,我们可以构建“Benchtop”PROLO,或者我们可以转到下一步 - 自定义DFM评论。

完整的DFM支持- 如果您的使命是创建强大,可靠和成本效益的设计,并且第一次获得它 - 我们有一名高级专业工程师(FAES)的员工,可作为您的制造顾问。我们的FAES将对您的设计提供全面的审查,包括分析DRC结果,对堆叠审查以及材料选项的讨论。最后的DFM报告将总结所有这些,并包括建议改进和最终的收益率。

T.he next step in DFM is a table top review of your design. We will invite you to one of our advanced technology manufacturing locations to meet the experts in person and spend a day reviewing your PCB design. Your visit will include a factory “walk through” that will be tailored to the design you are creating. During the walk through, you will be able to meet the people on the manufacturing floor, ask questions and get into the process.

生产工具

检查和仔细检查所有框

订单后,我们的预生产团队将通过将随附的CAD网表与设计数据进行比较来验证设计的电气完整性。此过程只需几分钟,但将验证设计数据,并将确认所有网络是否已连接,并且没有损坏的网或意外的短路。以下是我们看到的典型故障:

  • 隔离的散热器
  • Un-routed connections
  • 分裂飞机错误
  • 无意的短裤

堆叠和阻抗建模:A preliminary stackup may have been created for you during the quote stage, but it must be validated against the final production data. Our engineers will use our automated Stack Up Builder quickly create graphical stack up that clearly shows material types, dielectric thicknesses, overall thickness, copper weights impedance. The Stackup Builder will access our extensive library of rigid, flex and prepreg materials to create a stackup that will meet your specifications. Alternative stackups can be quickly generated if you are looking to compare cost, performance, or juggle material lead times. To help, we have programmed cost based constraints to help you determine the most economical options that meet your print requirements. Summit is committed to utilizing the latest technology in engineering systems to speed you through the tooling process with precise results.

在设计PCB时,请记住最佳堆叠的以下最佳实践,最终最可靠的PCB:

  • 设计多层PCB,偶数数量的层数
  • 电源和地面层应相对于板的中心平衡
  • 避免内层上的铜分布不均匀,因为它会影响董事会的平整度
  • 从PCB的中心线创建一致的介电厚度开口
  • 铜层应从董事会中心线平衡

Registration:所有峰会设施都利用了XACT®注册分析工具,为当今苛刻的登记要求提供课堂注册。

面板化– this is a critical factor to determining the cost of a printed circuit board. The objective it to maximize the greatest amount of parts on a production panel using industry standard panel sizes of 12”x18”, 16”x18”, 18”x24” and 21”x24”. PCBs will be placed on the panel individually or in a sub-panel, referred to as an array. An array is commonly used if volume pick and place assembly is required. Careful thought must go into the design of the array to ensure that the panel area is maximized. A poorly conceived array can impact the final cost of the PCB significantly.

T.he size of the panel must also include all necessary validation “coupons”. The coupons will be created according to customer and industry specifications and will be placed in the border area of the panel. Depending on the number and type of coupons required, borders can range from 0.5” to 2.0” or more to accommodate the coupons. The more coupons required, the less space on the panel for PCBs. If requested, Summit will provide a production panel layout for your review prior to manufacturing. A list of industry standard coupons is below.

优惠券 目的
A / B. 电镀孔/通过评估,尺寸,间距,注册,热应力
Conformance 返工仿真,粘接强度,剥离强度,介电耐压,水分/绝缘电阻
Impedance Validate impedance
D. 具有OM测试方法的可靠性测试测试方法IPC-TM-650 2.6.27
ist. Reliability testing with IST test methods IPC-TM-650 2.6.26
G 验证焊接面罩附着力
抵抗性 验证阻力

返回答题

提高信号完整性的成本效益手段

BROFFRING是一种经济有效的方法,可以提高信号完整性而不增加昂贵的额外的子层压结构。该过程消除了通过桶的不需要的部分,其可以在高速数据速率下或高频RF设计上引起信号反射。

好处:

  • 按级别的秩序减少确定性抖动,从而导致较低的误码率。
  • 增加es signal attenuation due to improved impedance matching.
  • 增加es EMI/EMC radiation from the stub end and increasing channel bandwidth.
  • 减少共振模式的激励和通过串联串扰。
  • 增加es additional lamination structures.
  • 通过比顺序层压更低的制造成本,最小化设计和布局冲击。
  • 改善微波RF性能。

设计注意事项:

  • 定义启动后水的侧面。
  • 定义“不得切割”(MNC)层。MNC层是必须保持连接的层,该层最接近的距离深度深度。
  • Keep back distance from MNC layer minimum is .005” with a tolerance of +/-.002”, standard depth is .010”. Please review the signal performance to determine which depth is required.
  • 后水直径通常是.008“在原始钻头上用于产生电镀的通孔。
  • Increase the copper clearance for the backdrilled layers an additional .004”.
  • MNC层必须至少为.010“远离PCB的后部侧的外层。这提供了到MNC层的最小距离,并提供到外层的最小绝缘距离。

铜均衡

创建统一分配

印刷电路板应设计有平衡的铜。铜平衡是实现成品印刷板的一致平整度所必需的。通过在PCB的每层跨越平衡的铜电镀分布,它还可以提高制造产量。平衡电镀可提高通孔铜电镀厚度的一致性,并有助于支撑镀层上的均匀导体和陆地厚度的稠度。在内层上,铜平衡有助于保持介电厚度。内层的均匀性在PCB上产生一致的总厚度。它减少了PCB的低压区域,如果未校正可能会导致处理问题并需要重新设计。

Copper Thickness and Resistance

增加e copper thickness for improved yields

外层铜厚度要求应审查为迹线宽度和间距下降.005“。外层起始铜将确定设计上的允许空间。较薄的基础铜可以是可能的更精细的空间。设计师必须考虑起始铜和孔铜电镀要求,以确定成品PCB上的外层铜。镀覆外层最小总铜的IPC规则是起始铜最小加上电镀孔壁中的最小铜。例如,如果外层以½盎司开始(处理后的最小厚度为0.000512“)并且孔中的要求是.001”,最小总层铜必须为.001512“或更大。(此信息可以在IPC-6012中找到)设计人员应尝试利用铜标注来满足电气需求,并考虑PCB的可制造性。

如果要控制起始铜,则在制造起始铜厚度上的简单状态。如果铜称为成品铜厚度峰会将选择最适用的起始铜,以达到您设计的最佳产量。

铜重量在每平方英尺盎司(取自IPC 1401)

挫败
指定
普通产业
术语
义务
厚度(米尔)
问: 9μm 0.34 mil
T. 12μm. 0.5毫升
H 1/2盎司 0.70 mil
m 3/4 oz 1.0 mil
1 1 oz 1.4 mil
2 2盎司 2.8 mil
3 3盎司 4.2 mil

应考虑到提高可制造性1/4,3 / 8和1/2盎司铜的规格。外层成品铜迹线比起始铜厚,因为它包括沉积在孔和表面上的电镀铜。在蚀刻过程中,仅蚀刻起始铜厚度,而不是镀表面铜。镀层层的总铜由起始铜确定,并且在电镀孔中需要铜电镀。通过审查IPC-6012表3-14可以确定总铜。

通过厚度和长度计算铜电阻:
电阻=(0.679×10-6欧姆/英寸)
(宽度x厚度英寸x长度)

例:
在细线技术中,使用0.5oz。铜,带5密耳的迹线和5英寸长的电阻率是:
((.679x 10-6)/(5×0.7 x10-6))x 5 =0.97Ω

HDI结构

在复杂的设计上使用盲人,埋藏和堆叠通过结构堆叠

Incorporating High Density Interconnect (HDI) structures is commonly utilized on advanced designs as a way to overcome space issues resulting from high I/O, fine pitch components. To achieve the density required in HDI designs, line width, spacing, hole diameters and pad sizes must all shrink. Reducing copper foil thickness on inner layers, reducing dielectric spacing to maintain low drill aspect ratios, incorporating via-in-pad and specifying the correct copper wrap are all critical factors in a successful design. However, for the most reliable structures, maintaining the following design guidelines will have the best results.

  • 将微通孔的堆叠限制为2堆叠,如果需要超过2层堆叠层,通过层次错开
  • 切勿将微米堆叠在埋藏的通孔顶部
  • 通过直径保持6密耳,带有12密耳的捕获垫
  • 为微疏松保持宽高比为0.75:1或更低
  • 在起始箔上指定.0002“铜包装
  • 铜填充微米填充
  • D.esign a D coupon that represents all via structures that can be tested for reliability using OM testing

Summit’s preferred method of testing HDI reliability is with OM testing. Read more on OM Testing.

通过填充

Create space for pads and improve reliability

Via in pad with non-conductive epoxy improves signal performance for high speed digital and RF microwave applications. Summit also has experience with conductive epoxy filled vias and plated solid with copper. Summit can assist you with a cost effective method to meet your high speed, thermal management needs. Utilizing the latest via fill equipment, Summit can achieve epoxy fill for 8 mil vias with 15:1 aspect ratios. To fill microvias, plated shut copper vias is our preferred approach. Here are some things to keep in mind when incorporating filled vias in your design:

  • Specify epoxy instead of metal based fill
  • 在外层微径上指定铜填充
  • 设计具有低启动箔,以减少整个序列电镀过程中的铜堆积

通过填充的好处

  • 通过减少捕获的空气或液体的风险来提高可靠性
  • 通过允许焊盘而不是狗骨设计,更紧密的BGA间距和更高密度互连。188金宝搏二维码峰会互连可以支持.25mm BGA要求。
  • 通过结构填充和堆叠可靠。
  • 上面填充通过更可靠的表面贴装和增加的装配产率的平面铜表面。
  • 增强的热耗散。